
SC16C850
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NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 2 — 11 November 2010
34 of 55
NXP Semiconductors
SC16C850
2.5 to 3.3 V UART with 128-byte FIFOs and IrDA encoder/decoder
[1]
7.17 Flow Control Trigger Level High (FLWCNTH)
This 8-bit register is used to store the receive FIFO high threshold levels to start/stop
transmission during hardware/software flow control.
Table 27 shows the FLWCNTH
[1]
7.18 Flow Control Trigger Level Low (FLWCNTL)
This 8-bit register is used to store the receive FIFO low threshold levels to start/stop
transmission during hardware/software flow control.
Table 28 shows the FLWCNTL
[1]
7.19 Clock Prescaler (CLKPRES)
This register hold values for the clock prescaler.
Table 27.
FLWCNTH register bits description
Bit
Symbol
Description
7:0
FLWCNTH[7:0]
This register stores the programmable HIGH threshold level for
hardware and software flow control for 128-byte FIFO
mode[1].
0x00 = trigger level is set to 1
0x01 = trigger level is set to 1
...
0x80 = trigger level is set to 128
Table 28.
FLWCNTL register bits description
Bit
Symbol
Description
7:0
FLWCNTL[7:0]
This register stores the programmable LOW threshold level for
hardware and software flow control for 128-byte FIFO
mode[1].
0x00 = trigger level is set to 1
0x01 = trigger level is set to 1
...
0x80 = trigger level is set to 128
Table 29.
Clock Prescaler register bits description
Bit
Symbol
Description
7:4
CLKPRES[7:4]
reserved
3:0
CLKPRES[3:0]
Clock Prescaler value. Reset to 0.